Interface design optimisation for WASP devices

Author

Bolouri, H. ; Hussaini, M.B.A. ; Hedge, S.J. ; Lea, R.M.

Author_Institution

Hertfordshire Univ., Hatfield, UK

fYear

1993

fDate

1993

Firstpage

223

Lastpage

232

Abstract

Details of defect and fault tolerance strategies used in the wafer interface blocks of wafer scale integration (WSI) associative string processor (WASP) devices are given. A structured approach to the design and optimization of redundant-path defect- and fault-tolerant signal distribution networks is presented. Monte Carlo simulations are used to analyze the success rate of various WASP signal distribution network topologies in the presence of randomly distributed defects. It is shown that the proposed signal distribution strategy lends itself well to high-speed recovery from in-operation failures.

Keywords

Monte Carlo methods; VLSI; fault tolerant computing; microprocessor chips; network topology; parallel architectures; Monte Carlo simulations; WASP devices; associative string processor; fault tolerance strategies; fault-tolerant signal distribution networks; high-speed recovery; redundant-path defect-networks; signal distribution network topologies; wafer interface blocks; wafer scale integration; Application specific processors; Chromium; Design optimization; Fault tolerance; Focusing; Image processing; Network topology; Signal analysis; Signal design; Signal processing;

fLanguage

English

Publisher

ieee

Conference_Titel

Wafer Scale Integration, 1993. Proceedings., Fifth Annual IEEE International Conference on

Conference_Location

San Francisco, CA, USA

Print_ISBN

0-7803-0867-0

Type

conf

DOI

10.1109/ICWSI.1993.255256

Filename

255256