DocumentCode
3434574
Title
A 0.8u 100-MHz 2-D DCT Core Processor
Author
Jang, Yi-Feng ; Kao, Jinn-Nang ; Yang, Jin-Shiang ; Huang, Po-Chuang
Author_Institution
Industrial Technology Research Institute, Taiwan
fYear
1994
fDate
21-23 June 1994
Firstpage
330
Lastpage
331
Keywords
Clocks; Communication industry; Computer industry; Discrete cosine transforms; Distributed algorithms; Frequency; Hardware; Image coding; Pipeline processing; Registers;
fLanguage
English
Publisher
ieee
Conference_Titel
Consumer Electronics, 1994. Digest of Technical Papers., IEEE 1994 International Conference on
Conference_Location
Rosemont, IL, USA
Print_ISBN
0-7803-1453-0
Type
conf
DOI
10.1109/ICCE.1994.582283
Filename
582283
Link To Document