Title :
Low S/D resistance FDSOI MOSFETs using polysilicon and CMP
Author :
Yin, Chunshan ; Chan, Victor W.C. ; Chan, Philip C.H.
Author_Institution :
Dept. of Electr. & Electron. Eng. Hong Kong Univ. of Sci. & Technol., China
Abstract :
In this paper, we report fully depleted silicon-on-insulator (FDSOI) MOSFETs with polysilicon (poly) raised source and drain (S/D) by using chemical mechanical polish (CMP). This poly-raised FDSOI MOSFET, with channel thickness of 30 nm and deposited poly thickness of 80 nm, has shown a 95% reduction in source and drain series resistance and 90% reduction in contact resistance, compared with conventional FDSOI devices with the same channel thickness and without polysilicon at the S/D region. Silicide can be used to further reduce the active resistance
Keywords :
MOSFET; chemical mechanical polishing; contact resistance; semiconductor device measurement; silicon-on-insulator; CMP; FDSOI MOSFETs; S/D region; S/D resistance; active resistance; channel thickness; chemical mechanical polish; contact resistance; deposited poly thickness; fully depleted SOI MOSFETs; fully depleted silicon-on-insulator MOSFETs; poly-raised FDSOI MOSFET; polysilicon; polysilicon raised source/drain; silicide; source/drain series resistance; Chemical technology; Contact resistance; Etching; Immune system; Lithography; MOSFETs; Parasitic capacitance; Protection; Silicides; Silicon on insulator technology;
Conference_Titel :
Electron Devices Meeting, 2001. Proceedings. 2001 IEEE Hong Kong
Conference_Location :
Hong Kong
Print_ISBN :
0-7803-6714-6
DOI :
10.1109/HKEDM.2001.946925
