Title :
Optimizing multipliers for WSI
Author :
Callaway, Thomas K. ; Swartzlander, Earl E., Jr.
Author_Institution :
Dept. of Electr. & Comput. Eng., Texas Univ., Austin, TX, USA
Abstract :
For arithmetic circuits, it is important to maximize the speed and to minimize the power consumption, which may be accomplished by minimizing the product of the delay and the power consumption. The authors discuss the speed and the number of logic transitions (a measure of power dissipation for static CMOS circuits) of several different parallel multipliers. The circuits are constructed with inverters and two- to four-input AND and OR gates. Extensive simulation is used to evaluate their switching characteristics, and the results of the simulations are used to rank the multipliers on speed, size, and the number of logic transitions.
Keywords :
CMOS integrated circuits; VLSI; logic gates; multiplying circuits; AND gates; OR gates; WSI; arithmetic circuits; delay; inverters; logic transitions; multipliers; parallel multipliers; power consumption; speed; static CMOS circuits; switching characteristics; Arithmetic; CMOS logic circuits; Circuit simulation; Energy consumption; Inverters; Logic circuits; Power dissipation; Switching circuits; Very large scale integration; Wafer scale integration;
Conference_Titel :
Wafer Scale Integration, 1993. Proceedings., Fifth Annual IEEE International Conference on
Conference_Location :
San Francisco, CA, USA
Print_ISBN :
0-7803-0867-0
DOI :
10.1109/ICWSI.1993.255270
