A HW/SW mixed mechanism to improve the dependability of a stack processor

In this paper we are presenting a journaling mechanism to improve dependability of a stack processor. This approach is based on a HW/SW mixed mechanism, using hardware error detection and software error correction. The SW correction is based on a rollback mechanism and relies on a journal. The journal is located between processor and the main memory in a way that all the data written into the main memory must pass through it. In case of error detection the rollback mechanism is executed in the journal. Therefore processor re-execute from the last sure states. In this way only validated data is written in the main memory. In order to evaluate the performance of our proposed architecture, the clocks per instruction are measured for different benchmarks in presence of high error rate.