Title :
Memory-based reasoning implemented by wafer scale integration
Author :
Yasunaga, Moritoshi ; Kitano, Hiroaki
Author_Institution :
Hitachi Ltd., Tokyo, Japan
Abstract :
The high robustness of memory-based reasoning (MBR), which is suitable for hardware implementation using wafer scale integration (WSI) technology, is demonstrated. A WSI MBR hardware design is proposed. Its robustness is evaluated by a WSI MBR simulator. The results show that defects or other fluctuations of device parameters have only minor impacts on the performances of the MBR. It is found that in order to obtain higher reasoning accuracy, the size of the MBR database is much more crucial than the computation resolution. The proposed WSI MBR processor takes advantage of benefits discovered in the simulation results.
Keywords :
VLSI; inference mechanisms; parallel machines; MBR database; WSI MBR hardware design; device parameters; memory-based reasoning; robustness; wafer scale integration; Circuit simulation; Computational modeling; Databases; Fluctuations; Hardware; Integrated circuit technology; Laboratories; Noise robustness; Silicon; Wafer scale integration;
Conference_Titel :
Wafer Scale Integration, 1993. Proceedings., Fifth Annual IEEE International Conference on
Conference_Location :
San Francisco, CA, USA
Print_ISBN :
0-7803-0867-0
DOI :
10.1109/ICWSI.1993.255278