A FPGA design of the I/Q signal combining for UHF RFID reader receiver

In this paper, a implementation of the I/Q signal combining for Ultra High Frequency (UHF) Radio Frequency Identification (RFID) reader receiver is presented. The design is concentrated on the low complexity and the low coast of the RFID reader. To reduce the complexity, area consumption and calculation time, the Loop Up Table (LUT) is applied. Only one multiplier and one divider which have many gates size is used for the low cost. The FPGA NCsim simulator is used to verify this design and it is tested on the reader platform based on FPGA. The simulation, design results and the performance results of the reader receiver using the I/Q signal combining is presented.