Title :
Dielectric breakdown in high-K metal gate: Measurement, device level model and application to circuit
Author :
Cacho, F. ; Angot, D. ; Saliva, M. ; Mora, P. ; Rafik, M. ; Federspiel, Xavier ; Roy, Didier ; Huard, Vincent
Author_Institution :
STMicroelectron., Crolles, France
Abstract :
Gate oxide breakdown is an important reliability issue. This mechanism is widely investigated at device level but the development of a compact model and the assessment at circuit level is much more complex to handle. We first characterize soft and hard breakdown with highlighting the different electrical signatures and sign change of the ratio source drain current. Then a transistor-level model of breakdown is presented. The model is calibrated for a large range of breakdown severity. Finally the model is used at circuit level. The impact of breakdown on both static current and frequency of ring oscillator is discussed.
Keywords :
electric breakdown; high-k dielectric thin films; measurement systems; reliability; circuit level; compact model; device level model; dielectric breakdown; electrical signatures; gate oxide breakdown; hard breakdown; high-k metal gate; measurement model; ratio source drain current; reliability issue; ring oscillator; sign change; soft breakdown; static current; transistor-level model; Electric breakdown; Integrated circuit modeling; Logic gates; MOS devices; Reliability; Semiconductor device modeling; Stress;
Conference_Titel :
Integrated Reliability Workshop Final Report (IRW), 2012 IEEE International
Conference_Location :
South Lake Tahoe, CA
Print_ISBN :
978-1-4673-2749-7
DOI :
10.1109/IIRW.2012.6468940
