DocumentCode :
3435486
Title :
Highly scalable parallel parametrizable architecture of the motion estimator
Author :
Cmar, R. ; Vernalde, S.
Author_Institution :
Dept. of Microelectron., FEI STU, Bratislava, Slovakia
fYear :
1997
fDate :
17-20 Mar 1997
Firstpage :
208
Lastpage :
212
Abstract :
In this paper a parametrizable architecture of a motion estimator (ME) is presented. The ME is designed as a generic full pixel calculation module which can be adopted for different video standards. The parameters by which the ME is described allow for a variety of architecture implementations. The parameters specify the level of parallelism reflected by multiple allocation of computational resources, and the use of configurable cache memories. The obtained VHDL description of the ME module is well suited for VLSI implementation
Keywords :
VLSI; data compression; digital signal processing chips; hardware description languages; motion estimation; parallel architectures; video coding; VHDL description; VLSI implementation; computational resources; configurable cache memories; generic full pixel calculation module; motion estimator; multiple allocation; parallel parametrizable architecture; video standards; Cache memory; Computer architecture; Concurrent computing; Hardware; Microelectronics; Motion estimation; Parallel processing; Resource management; Strips; Very large scale integration;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
European Design and Test Conference, 1997. ED&TC 97. Proceedings
Conference_Location :
Paris
ISSN :
1066-1409
Print_ISBN :
0-8186-7786-4
Type :
conf
DOI :
10.1109/EDTC.1997.582360
Filename :
582360
Link To Document :
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