Title :
Circuit design techniques for deep submicron technologies
Abstract :
This article presents design techniques for deep submicron integrated circuits. It includes a discussion of both chip-level design challenges (capacitive and inductive noise, domino vs. static design styles, dual VT transistors and clock distribution) and system-level design challenges
Keywords :
clocks; integrated circuit design; integrated circuit noise; capacitive noise; chip-level design; clock distribution; deep submicron technology; domino design; dual VT transistor; inductive noise; integrated circuit design; static design; system-level design; Circuit synthesis; Very large scale integration;
Conference_Titel :
Circuits and Systems, 2001. Tutorial Guide: ISCAS 2001. The IEEE International Symposium on
Conference_Location :
Sydney, NSW
Print_ISBN :
0-7803-7113-5
DOI :
10.1109/TUTCAS.2001.946982
