Architectural exploration and optimization for counter based hardware address generation

Author

Miranda, Miguel ; Kaspar, Martin ; Catthoor, Francky ; Man, Hugo De

Author_Institution

IMEC, Leuven, Belgium

fYear

1997

fDate

17-20 Mar 1997

Firstpage

293

Lastpage

298

Abstract

A set of automated system level techniques is presented for architectural exploration and optimization of counter based address generation units in real time signal processing systems. The goal is to explore different architectural alternatives available when mapping array references in order to select the most promising ones in area cost. The techniques are demonstrated on realistic test-vehicles, showing that architectural decision at early stages of the design process, can have a very large impact on the resulting area figure

Keywords

counting circuits; distributed memory systems; memory architecture; optimisation; real-time systems; signal processing; architecture; area figure; array reference mapping; automated system level technique; counter; design; hardware address generation unit; optimization; real time signal processing; test vehicle; Bandwidth; Constraint optimization; Costs; Counting circuits; Hardware; Memory management; Real time systems; Signal generators; Signal processing; Signal processing algorithms;

fLanguage

English

Publisher

ieee

Conference_Titel

European Design and Test Conference, 1997. ED&TC 97. Proceedings

Conference_Location

Paris

ISSN

1066-1409

Print_ISBN

0-8186-7786-4

Type

conf

DOI

10.1109/EDTC.1997.582373

Filename

582373