A multi level functional verification of multistage interconnection network for MPSOC

Network on chip (NOC) has emerged as a promising alternative to ensure communication for Multiprocessor systems on chip (MPSoC). This paper proposes a hybrid verification approach of Delta multistage interconnection networks for MPSoC. At the generic level, we propose a formal specification of the network in the ACL2 theorem proving environment. We will ensure the soundness of our verification approach by using programmable logic circuits for fast performance verification of Delta MIN. We thus show the utility of the hybrid approach to give a more realistic model describing the communication architectures.