Title :
A gridless multi-layer router for standard cell circuits using CTM cells
Author :
Tseng, Hsiao-Ping ; Sechen, Carl
Author_Institution :
Dept. of Electr. Eng., Washington Univ., Seattle, WA, USA
Abstract :
We present a gridless multi-layer router suitable for standard cell circuits using central terminal model (CTM) cells. A CTM cell has pins in the middle which split the over-the-cell routing region into top and bottom parts. Our router routes nets in both the channel (if needed) and over-the-cell. The router uses a combined constraint graph and tile expansion algorithm. It achieves channelless solutions for the Primary1 circuit by routing over the cell in three layers. For classical channel routing examples, it achieves solutions at density for Deutsch´s difficult example in two, three, four and five metal layers. It also generates equal or better results compared to the best of the previous channel routers for all the examples we have tried
Keywords :
VLSI; circuit layout CAD; computational complexity; graph theory; integrated circuit layout; network routing; CTM cells; Primary1 circuit; central terminal model cells; channel routing; channelless solutions; constraint graph; gridless multi-layer router; over-the-cell routing region; standard cell circuits; tile expansion algorithm; Circuits; Clocks; Design automation; Pins; Routing; Tiles; Very large scale integration; Wires; Wiring;
Conference_Titel :
European Design and Test Conference, 1997. ED&TC 97. Proceedings
Conference_Location :
Paris
Print_ISBN :
0-8186-7786-4
DOI :
10.1109/EDTC.1997.582377