DocumentCode :
3435819
Title :
Exploring performance-power trade-offs for look-up tables in SRAM-based FPGAs
Author :
Echeverría, Pedro ; López-Vallejo, Marisa ; Bolognesi, Walter ; López-Barrio, Carlos
Author_Institution :
Dept. of Electron. Eng., Univ. Politec. de Madrid, Madrid, Spain
fYear :
2009
fDate :
13-16 Dec. 2009
Firstpage :
423
Lastpage :
426
Abstract :
Current trend on FPGAs is to increase the number of inputs of the LUT up to six inputs to improve resource utilization. In this work we have analyzed the impact of the inputs expansion in two different architectures, memory-based and multiplexer-based, considering area, performance and power. A new memory-based architecture is presented based on the use of a 7-transistor cell and dedicated reading and writing circuits. The experimental results carried out demonstrate that for a six input LUT, our architecture outperforms the traditional multiplexer-based LUT, which is commonly considered the optimum architecture.
Keywords :
SRAM chips; field programmable gate arrays; table lookup; FPGA; SRAM; look-up table; memory-based architecture; multiplexer-based architecture; Circuits; Field programmable gate arrays; Logic; Memory architecture; Performance analysis; Random access memory; Read-write memory; Resource management; Routing; Table lookup;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Electronics, Circuits, and Systems, 2009. ICECS 2009. 16th IEEE International Conference on
Conference_Location :
Yasmine Hammamet
Print_ISBN :
978-1-4244-5090-9
Electronic_ISBN :
978-1-4244-5091-6
Type :
conf
DOI :
10.1109/ICECS.2009.5410900
Filename :
5410900
Link To Document :
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