BIST reseeding with very few seeds

Author

Al-Yamani, Ahmad A. ; Mitra, Subbasish ; McCluskey, Edward J.

Author_Institution

Center for Reliable Comput., Stanford Univ., CA, USA

fYear

2003

fDate

27 April-1 May 2003

Firstpage

69

Lastpage

74

Abstract

Reseeding is used to improve the fault coverage of pseudo-random testing. The seed corresponds to the initial state of the LFSR before filling the scan chain. The number of deterministic seeds required is directly proportional to the tester storage or hardware overhead requirement. In this paper, we present an algorithm for seed ordering to minimize the number of seeds required to cover a set of deterministic test patterns. Our technique is applicable whether seeds are loaded from the tester or encoded on chip. Simulations show that, when compared to random ordering, the technique reduces seed storage or hardware overhead by up to 80%. The seeds we use are deterministic so 100% SSF fault coverage can be achieved. Also, the technique we present is fault-model independent.

Keywords

boundary scan testing; built-in self test; circuit simulation; integrated circuit design; integrated circuit testing; logic design; logic simulation; logic testing; random sequences; shift registers; BIST reseeding; LFSR; LFSR initial state; SSF fault coverage; deterministic seeds; deterministic test pattern set; fault-model independent technique; hardware overhead requirement; linear feedback shift register; low seed number BIST; on chip encoding; pseudo-random testing; scan chain; seed number minimization; seed ordering; tester loaded seeds; tester storage requirement; Built-in self-test; Testing; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Test Symposium, 2003. Proceedings. 21st

ISSN

1093-0167

Print_ISBN

0-7695-1924-5

Type

conf

DOI

10.1109/VTEST.2003.1197635

Filename

1197635