DocumentCode :
3435865
Title :
A design methodology for high-performance and low-leakage fixed-point transpose FIR filters
Author :
Bekiaris, Dimitris ; Xydis, Sotiris ; Economakos, George ; Pekmestzi, Kiamal
Author_Institution :
Dept. of Electr. & Comput. Eng., Nat. Tech. Univ. of Athens, Athens, Greece
fYear :
2009
fDate :
13-16 Dec. 2009
Firstpage :
415
Lastpage :
418
Abstract :
This paper addresses the low leakage implementation of fixed-point transpose FIR filters, considering dual-Vth CMOS standard-cell libraries. Specifically, we introduce a design flow, based on a novel two-level selection algorithm, which replaces low-Vth Multiplication-Addition units by their high-Vth counterparts, taking into account the timing slack of each unit and the word-level binary representation of the units´ coefficients. The proposed methodology is evaluated on an 8-tap and a 16-tap transpose FIR filters. Post-layout power results demonstrate leakage improvements ranging from 6.69-25.85% for several clock period constraints, compared to the low-Vth FIR implementations. Also, reduction of up to 12.35% is measured in overall power dissipation.
Keywords :
CMOS integrated circuits; FIR filters; integrated circuit design; clock period constraints; design flow; design methodology; dual-Vth CMOS standard-cell library; fixed-point transpose FIR filters; leakage improvements; low-Vth multiplication-addition units; post-layout power; power dissipation; timing slack; two-level selection algorithm; word-level binary representation; CMOS technology; Design methodology; Electronic mail; Equations; Finite impulse response filter; Libraries; Sleep; Subthreshold current; Threshold voltage; Tunneling;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Electronics, Circuits, and Systems, 2009. ICECS 2009. 16th IEEE International Conference on
Conference_Location :
Yasmine Hammamet
Print_ISBN :
978-1-4244-5090-9
Electronic_ISBN :
978-1-4244-5091-6
Type :
conf
DOI :
10.1109/ICECS.2009.5410902
Filename :
5410902
Link To Document :
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