Title :
Analysis and design of optimal combinational compactors [logic test]
Author :
Wohl, Peter ; Huisman, Leendert
Author_Institution :
Synopsys Inc., Williston, VT, USA
fDate :
27 April-1 May 2003
Abstract :
Scan and logic built-in self-test (BIST) are increasingly used to reduce test cost. In these test architectures, many internal signals are observed through a small number of output pins or into a small signature analyzer, requiring a combinational space compactor. This paper analyzes the basic requirements of compactors to support efficient test and diagnosis, focusing on practical compactors where all inputs have a fanout of two. We show how graph theory can be used to model compactors and design compactors with robust non-aliasing properties that have minimal area and delay overhead and are independent of the test set, the fault model, and the circuit tested.
Keywords :
boundary scan testing; built-in self test; combinational circuits; fault diagnosis; graph theory; integrated circuit design; integrated circuit testing; logic design; logic testing; IC test; area overhead; built-in self-test; combinational compactor optimization; combinational space compactor; compactor nonaliasing properties; delay overhead; fault diagnosis; fault model; graph theory; input fanout; logic BIST; scan testing; signature analyzer; test set independence; Automatic testing; Built-in self-test; Circuit testing; Costs; Delay; Graph theory; Logic testing; Pins; Robustness; Signal analysis;
Conference_Titel :
VLSI Test Symposium, 2003. Proceedings. 21st
Print_ISBN :
0-7695-1924-5
DOI :
10.1109/VTEST.2003.1197639
