Automatic configuration generation for FPGA interconnect testing

Author

Tahoori, Mehdi Baradaran ; Mitra, Subhasish

Author_Institution

Centerfor Reliable Comput., Stanford Univ., CA, USA

fYear

2003

fDate

27 April-1 May 2003

Firstpage

134

Lastpage

139

Abstract

We present a new automatic test configuration generation technique for manufacturing testing of interconnect network of SRAM-based FPGA architectures. The technique guarantees detection of open and bridging faults in all wiring channels and programmable switches in the interconnects. Only 8 test configurations are required to achieve 100% coverage of stuck-open, stuck-closed, open and bridging faults in the interconnects of Xilinx Virtex FPGAs.

Keywords

automatic test pattern generation; field programmable gate arrays; integrated circuit interconnections; integrated circuit testing; logic testing; production testing; ATPG; FPGA interconnect testing; SRAM-based FPGA architectures; Xilinx Virtex FPGAs; automatic test configuration generation; bridging fault detection; manufacturing testing; open fault detection; programmable switches; stuck-closed faults; stuck-open faults; wiring channels; Automatic testing; Circuit faults; Field programmable gate arrays; Integrated circuit interconnections; Manufacturing; Programmable logic arrays; Routing; Switches; Wires; Wiring;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Test Symposium, 2003. Proceedings. 21st

ISSN

1093-0167

Print_ISBN

0-7695-1924-5

Type

conf

DOI

10.1109/VTEST.2003.1197644

Filename

1197644