A 1.21V, 100mA, 0.1µF–10µF output capacitor low drop-out voltage regulator for SoC applications

Author

Garimella, Annajirao ; Furth, Paul M.

Author_Institution

Klipsch Sch. of Electr. & Comput. Eng., New Mexico State Univ., Las Cruces, NM, USA

fYear

2009

fDate

13-16 Dec. 2009

Firstpage

375

Lastpage

378

Abstract

A 1.21 V output, 100 mA, 0.1 μF-10 μF output capacitor, ESR-independent, low voltage, low drop-out voltage regulator for portable power applications is designed and fabricated in a 0.5 μm CMOS process with an area of 0.22 mm². The use of a wide-range output capacitor LDO enables reduced target system PCB size and bill of materials (BOM). A 0.05%/V line regulation, 0.001%/mA load regulation with 220 mV drop-out is measured. LDO-specific pole-zero and optimal stability analyses are detailed.

Keywords

CMOS integrated circuits; logic design; system-on-chip; voltage regulators; CMOS process; LDO-specific pole-zero; PCB size; SoC application; bill of materials; capacitance 0.1 μF to 10 μF; current 100 mA; low drop-out voltage regulator; optimal stability analysis; output capacitor; portable power application; size 0.5 micron; voltage 1.21 V; voltage 220 mV; Application software; Bills of materials; Capacitors; Circuits; Energy management; Low voltage; Phasor measurement units; Power system management; Regulators; Resistors;

fLanguage

English

Publisher

ieee

Conference_Titel

Electronics, Circuits, and Systems, 2009. ICECS 2009. 16th IEEE International Conference on

Conference_Location

Yasmine Hammamet

Print_ISBN

978-1-4244-5090-9

Electronic_ISBN

978-1-4244-5091-6

Type

conf

DOI

10.1109/ICECS.2009.5410912

Filename

5410912