DocumentCode :
3436094
Title :
On maximizing the fault coverage for a given test length limit in a synchronous sequential circuit
Author :
Pomeranz, Irith ; Reddy, Sudhakar M.
Author_Institution :
Sch. of Electr. & Comput. Eng, Purdue Univ., West Lafayette, IN, USA
fYear :
2003
fDate :
27 April-1 May 2003
Firstpage :
173
Lastpage :
178
Abstract :
When storage requirements or limits on test application time do not allow a complete (compact) test set to be used for a circuit, a partial test set that detects as many faults as possible is required. Motivated by this application, we address the following problem. Given a test sequence T of length L for a synchronous sequential circuit and a length MS of length at most M such that the fault coverage of TS is maximal. A similar problem was considered before for combinational and scan circuits, and solved by test ordering. Test ordering is not possible with the single test sequence considered here. We solve this problem by using a vector omission process that allows the length of the sequence T to be reduced while allowing controlled reductions in the number of detected faults. In this way, it is possible to obtain a sequence TS that has the desired length and a maximal fault coverage.
Keywords :
circuit simulation; fault location; fault simulation; integrated circuit testing; logic simulation; logic testing; sequential circuits; fault coverage maximization; fault detection; partial test set; sequence length reduction; synchronous sequential circuit; test sequence length limiting; vector omission process; Application software; Circuit faults; Circuit testing; Cities and towns; Combinational circuits; Electrical fault detection; Fault detection; Sequential analysis; Sequential circuits;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
VLSI Test Symposium, 2003. Proceedings. 21st
ISSN :
1093-0167
Print_ISBN :
0-7695-1924-5
Type :
conf
DOI :
10.1109/VTEST.2003.1197648
Filename :
1197648
Link To Document :
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