DocumentCode :
3436157
Title :
A novel methodology for designing TSC networks based on the parity bit code
Author :
Bolchini, C. ; Salice, F. ; Sciuto, D.
Author_Institution :
Dipartimento di Elettronica e Inf., Politecnico di Milano, Italy
fYear :
1997
fDate :
17-20 Mar 1997
Firstpage :
440
Lastpage :
444
Abstract :
Combinational circuits encoded with the parity bit code can be defined TSC if and only if the number of the observed outputs modified by any admissible fault (fault observability) is odd. The methodology presented in this paper allows the use of the parity bit code by synthesizing an encoded network and then modifying the observability of each fault f∈F by introducing an auxiliary output, if necessary. In particular, the function implementing the auxiliary output allows an odd observability every time the observability of an internal node in the initial realization is even
Keywords :
automatic testing; combinational circuits; error detection codes; logic design; network synthesis; observability; parity; TSC network design; auxiliary output; combinational circuit; fault observability; parity bit code; totally self-checking circuit; Built-in self-test; Circuit faults; Circuit synthesis; Design methodology; Electrical fault detection; Fault detection; Logic devices; Logic testing; Network synthesis; Observability;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
European Design and Test Conference, 1997. ED&TC 97. Proceedings
Conference_Location :
Paris
ISSN :
1066-1409
Print_ISBN :
0-8186-7786-4
Type :
conf
DOI :
10.1109/EDTC.1997.582397
Filename :
582397
Link To Document :
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