Title :
Testing scheme for IC´s clocks
Author :
Favalli, Michele ; Metra, Cecilia
Author_Institution :
DEIS, Bologna Univ., Italy
Abstract :
This paper proposes a testing scheme to detect abnormal skews between clock signals inside digital synchronous ICs. The scheme is based on a new CMOS sensing circuit whose compactness and testability with respect to a large set of failures make it suitable for both off-line and on-line testing
Keywords :
CMOS digital integrated circuits; clocks; integrated circuit testing; CMOS sensing circuit; clock signal; digital synchronous IC; failure; off-line testing; on-line testing; skew; testing; Circuit faults; Circuit testing; Clocks; Degradation; Delay; Electrical fault detection; Fault detection; Logic testing; Routing; Sampling methods;
Conference_Titel :
European Design and Test Conference, 1997. ED&TC 97. Proceedings
Conference_Location :
Paris
Print_ISBN :
0-8186-7786-4
DOI :
10.1109/EDTC.1997.582398
