DocumentCode :
3436333
Title :
Die-to-die and within-die fabrication variation of 65nm CMOS technology PMOS transistors
Author :
Khan, Adnan Ahmed ; Ohnari, Y. ; Dutta, Arin ; Singh, Sushil ; Miura-Mattausch, M. ; Mattausch, Hans Jurgen
Author_Institution :
IIT Hyderabad, Hyderabad, India
fYear :
2013
fDate :
17-19 Jan. 2013
Firstpage :
1
Lastpage :
6
Abstract :
Study and understanding of transistor and circuit variations caused by the fabrication process has become an important factor for integrated circuits as the device dimensions become smaller. Effects on clock frequency and IC performance caused by die-to-die and within-die variations have made it important to incorporate process variations in circuit simulators to correctly model the working of the present IC technology. This paper demonstrates the microscopic parameter variation modeling of die-to-die and within-die variations for 65nm CMOS fabrication technology by using the HiSIM surface-potential-based compact model. It is found that for accurate variation modeling of Vth and Ion from die-to-die and within-die primary consideration of only four parameters, namely substrate doping (NSUBC), pocket-implantation doping (NSUBP), carrier mobility degradation due to gate-interface roughness (MUESR1) and channel length change (XLD) is sufficient. In addition to these, modeling of within-die variation requires inclusion of a small variation for a fifth parameter describing the depletion charge contribution for the effective-electric field (NDEP). Variation analysis is done for wide p-MOSFETs (W=10μm) as a function of gate length.
Keywords :
CMOS integrated circuits; MOSFET; electric fields; semiconductor doping; CMOS technology PMOS transistors; HiSIM surface-potential-based compact model; IC performance; MUESR1; NDEP; NSUBC; NSUBP; XLD; carrier mobility degradation; channel length change; circuit simulators; clock frequency; depletion charge contribution; device dimensions; die-to-die fabrication variation; effective-electric field; gate length; gate-interface roughness; integrated circuits; microscopic parameter variation modeling; p-MOSFET; pocket-implantation doping; size 10 mum; size 65 nm; substrate doping; within-die fabrication variation; Fabrication; Integrated circuit modeling; Logic gates; MOSFET circuits; Microscopy; Semiconductor device modeling; Semiconductor process modeling; MOSFET; compact model; die-to-die; fabrication variation; microscopic parameters; within-die;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Electronics, Computing and Communication Technologies (CONECCT), 2013 IEEE International Conference on
Conference_Location :
Bangalore
Print_ISBN :
978-1-4673-4609-2
Type :
conf
DOI :
10.1109/CONECCT.2013.6469286
Filename :
6469286
Link To Document :
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