Title :
A PLL configuration for reducing both incoming and inherent jitters
Author :
Kobayashi, Fuminori ; Egashira, Yuhta ; Kondoh, Hitoshi
Author_Institution :
Dept. of Syst. Design & Inf., Kyushu Inst. of Technol., Iizuka, Japan
Abstract :
In order to reduce jitters, both incoming and inherent, this article proposes a novel configuration. Feed-forward compensator improves jitter filtration, free from constraints on loop gain for reducing inherent jitters. Its effectiveness is verified on a prototype implemented on an FPGA, and experiments as a multiply-by-50 synthesizer result in 30-times reduction of inherent jitters and in halving of incoming jitters.
Keywords :
feedforward; field programmable gate arrays; jitter; phase locked loops; FPGA; PLL configuration; feed-forward compensator; field programmable gate arrays; incoming jitter; inherent jitter; jitter filtration; loop gain; multiply-by-50 synthesizer result; phase locked loop; Bandwidth; Control theory; Feedforward systems; Field programmable gate arrays; Filtration; Frequency synthesizers; Informatics; Jitter; Phase locked loops; Voltage-controlled oscillators;
Conference_Titel :
Electronics, Circuits, and Systems, 2009. ICECS 2009. 16th IEEE International Conference on
Conference_Location :
Yasmine Hammamet
Print_ISBN :
978-1-4244-5090-9
Electronic_ISBN :
978-1-4244-5091-6
DOI :
10.1109/ICECS.2009.5410931
