DocumentCode :
3436531
Title :
SOC test scheduling using simulated annealing
Author :
Zou, Wei ; Reddy, Sudhakar M. ; Pomeranz, Irith ; Huang, Yu
Author_Institution :
Dept. of Elec. & Comput. Eng., Iowa Univ., Iowa City, IA, USA
fYear :
2003
fDate :
27 April-1 May 2003
Firstpage :
325
Lastpage :
330
Abstract :
We propose an SOC test scheduling method based on simulated annealing. In our method, the test scheduling is formulated as a two-dimensional bin packing problem (rectangle packing) and a data structure called a sequence pair is used to represent the placement of the rectangles. Simulated annealing is used to find the optimal test schedule by altering an initial sequence pair and changing the width of the core wrapper. We also propose a method of wrapper design for cores without internal scan chains. Experiments are conducted on ITC´02 benchmarks, showing that overall the proposed method provides better solutions compared to earlier methods.
Keywords :
data structures; integrated circuit testing; scheduling; simulated annealing; system-on-chip; ITC´02 benchmarks; SOC test scheduling; core wrapper; data structure; initial sequence pair; placement; rectangle packing; sequence pair; simulated annealing; test scheduling method; two-dimensional bin packing problem; wrapper design; Simulated annealing; Testing; Very large scale integration;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
VLSI Test Symposium, 2003. Proceedings. 21st
ISSN :
1093-0167
Print_ISBN :
0-7695-1924-5
Type :
conf
DOI :
10.1109/VTEST.2003.1197670
Filename :
1197670
Link To Document :
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