DocumentCode :
3436550
Title :
Layered approach to designing system test interfaces
Author :
Chiang, Man Wah ; Zilic, Zeljko
Author_Institution :
McGill Univ., Montreal, Que., Canada
fYear :
2003
fDate :
27 April-1 May 2003
Firstpage :
331
Lastpage :
336
Abstract :
The layered system design approach has shown its strength in the design of the network and other complex systems. In this paper, we apply this approach to the design of system testing interfaces. The system is partitioned into layers to maximize reuse, and ease the development. In this paper, we demonstrate this methodology by designing a low-overhead testing interface and circuitry for the Infiniband Architecture (IBA).
Keywords :
automatic testing; boundary scan testing; integrated circuit testing; system-on-chip; Infiniband Architecture; SoCs; layered approach; low-overhead testing interface; reuse; system test interfaces; system testing interfaces; Circuit testing; Control systems; Costs; Design methodology; Integrated circuit interconnections; Integrated circuit testing; Logic testing; Protocols; Registers; System testing;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
VLSI Test Symposium, 2003. Proceedings. 21st
ISSN :
1093-0167
Print_ISBN :
0-7695-1924-5
Type :
conf
DOI :
10.1109/VTEST.2003.1197671
Filename :
1197671
Link To Document :
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