DocumentCode :
3436570
Title :
Diagnosis of delay defects using statistical timing models
Author :
Krstic, Angela ; Wang, Li.-C. ; Cheng, Kwang-Ting ; Liou, Jing-Jia
Author_Institution :
Dept. of Electr. & Comput. Eng., California Univ., Santa Barbara, CA, USA
fYear :
2003
fDate :
27 April-1 May 2003
Firstpage :
339
Lastpage :
344
Abstract :
In this paper, we study the problem of delay defect diagnosis based on statistical timing models. We propose a diagnosis algorithm that can effectively utilize statistical timing information based upon single defect assumption. We evaluate its performance and its applicability to single as well as multiple defect scenarios via statistical defect injection and simulation. With a statistical timing analysis framework developed in the past, we demonstrate the new concept in statistical delay defect diagnosis, and discuss experimental results using benchmark circuits.
Keywords :
VLSI; automatic test pattern generation; fault diagnosis; integrated circuit testing; logic testing; statistical analysis; timing; benchmark circuits; delay defects; diagnosis algorithm; multiple defect scenarios; single defect assumption; single defect scenarios; statistical defect injection; statistical timing information; statistical timing models; Circuit faults; Circuit noise; Circuit simulation; Delay effects; Dictionaries; Fault diagnosis; Logic testing; Manufacturing processes; Random variables; Timing;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
VLSI Test Symposium, 2003. Proceedings. 21st
ISSN :
1093-0167
Print_ISBN :
0-7695-1924-5
Type :
conf
DOI :
10.1109/VTEST.2003.1197672
Filename :
1197672
Link To Document :
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