Parallel SOLVE for direct circuit simulation on a transputer array

Sparse matrix solution (SOLVE) is a dominant part of the total execution time in a circuit simulation program such as SPICE. For simulation of modern VLSI circuit designs, it is important that this time be reduced. This paper presents a block partitionable sparse matrix solution algorithm in which a matrix is divided into equal size blocks, and blocks are assigned to different processors for parallel execution. The algorithm developed in this work exploits sparsity at the block level as well as within a non-zero block. An efficient mapping scheme to assign matrix blocks to processors is developed which maximizes concurrency and minimizes communication between processors. Associated reordering and efficient sparse storage schemes are also developed. An implementation of this parallel algorithm is carried out on a Transputer processor array which plugs into a PC bus. The sparse matrix solver is tested on matrices generated from a transistor-level expansion of ISCAS-85 benchmark logic circuits. Good speedup is obtained for all benchmark matrices up to the number of Transputers available