Title :
An asynchronous architecture for digital signal processors
Author :
Karthikeyan, M.R. ; Nandy, S.K.
Author_Institution :
Texas Instrum. India Ltd., Bangalore, India
Abstract :
Summary form only given. We propose an asynchronous architecture for digital signal processors. This is based on a modification of the counterflow pipeline. In addition to registers, we apply the counterflow technique to memory operands as well. This results in an asynchronous architecture with good performance potential for DSP. We describe the architecture below
Keywords :
asynchronous circuits; computer architecture; digital signal processing chips; pipeline processing; DSP; asynchronous architecture; counterflow pipeline; digital signal processors; memory operand; registers; Computer aided instruction; Computer architecture; Computer interfaces; Digital signal processing; Digital signal processors; Instruments; Memory management; Pipelines; Read-write memory; Registers;
Conference_Titel :
European Design and Test Conference, 1997. ED&TC 97. Proceedings
Conference_Location :
Paris
Print_ISBN :
0-8186-7786-4
DOI :
10.1109/EDTC.1997.582428
