A double-sampled hybrid CT/DT SMASH ΣΔ modulator for wideband applications

This paper presents a novel hybrid continuous-time (CT) and discrete-time (DT) sturdy multi-stage noise shaping (SMASH) ΣΔ modulator architecture. The double-sampling technique is employed in the DT second stage modulator to reduce the power consumption of the overall modulator. A flat and unity STFs are used in the first and second stage modulators, respectively, to reduce the output swing of the analog building blocks without influencing the inherent anti-aliasing behavior of the first stage CT modulator. As a design example, the proposed SMASH 2-2 modulator is designed in a 90 nm CMOS technology with 1 V power supply. HSPICE simulation results show a signal-to-noise plus distortion ratio (SNDR) of 80.4 dB in 12.5 MHz bandwidth with 17 mW power consumption while operating at 200 MHz sampling frequency.