DocumentCode :
3436825
Title :
Optimal scheduling for fast systolic array implementations
Author :
Ozimek, I. ; Verlic, R. ; Tasic, J.
Author_Institution :
Jozef Stefan Inst., Ljubljana Univ., Slovenia
fYear :
1997
fDate :
17-20 Mar 1997
Firstpage :
620
Abstract :
Summary form only given. Certain real-time applications (e.g. signal filtering and processing in a digital communication system) require the use of a special massively parallel computing structure, called the systolic array structure, to achieve acceptable performance. To implement an algorithm this way, we need a mapping procedure to map a set of equations, which describe the algorithm, to the systolic army. This mapping consists of scheduling (i.e. time mapping, mapping of each DG node to a particular time instant) and space mapping (mapping of each DG node to a systolic array cell). In the paper we propose a new approach to scheduling of complicated algorithms (that are described by a set of equations, fulfilling the requirement of regularity i.e. constant dependence vectors). It takes into account the exact computational requirements of the basic arithmetic operations used and yields near optimal scheduling from the viewpoint of execution speed of the resulting implementation
Keywords :
VLSI; parallel algorithms; pipeline processing; processor scheduling; real-time systems; systolic arrays; arithmetic operations; complicated algorithms; computational requirements; execution speed; fast systolic array implementations; mapping procedure; optimal scheduling; real-time applications; Digital communication; Digital filters; Equations; Filtering; Optimal scheduling; Parallel processing; Processor scheduling; Real time systems; Signal processing; Systolic arrays;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
European Design and Test Conference, 1997. ED&TC 97. Proceedings
Conference_Location :
Paris
ISSN :
1066-1409
Print_ISBN :
0-8186-7786-4
Type :
conf
DOI :
10.1109/EDTC.1997.582433
Filename :
582433
Link To Document :
بازگشت