Title :
Low power CMOS clock buffer
Author :
Khoo, Kei-Yong ; Willson, Alan N., Jr.
Author_Institution :
Integrated Circuits & Syst. Lab., California Univ., Los Angeles, CA, USA
fDate :
30 May-2 Jun 1994
Abstract :
Modern high speed CMOS processors using on-chip phase-locked-loops often require a clock buffer with stringent specifications on the signal´s rise time and fall time rather than on the buffer´s delay time. For these applications, we propose a low power CMOS clock buffer that momentarily tri-states its output to minimize its power dissipation and its area requirement below those that are achievable by the traditional tapered CMOS buffers
Keywords :
CMOS digital integrated circuits; buffer circuits; timing circuits; area requirement; high speed CMOS processors; low power CMOS clock buffer; onchip PLLs; output tristates; phase-locked-loops; power dissipation; signal fall time; signal rise time; CMOS integrated circuits; Clocks; Delay; High speed integrated circuits; Inverters; Latches; Minimization; Phase locked loops; Power dissipation; Power system reliability;
Conference_Titel :
Circuits and Systems, 1994. ISCAS '94., 1994 IEEE International Symposium on
Conference_Location :
London
Print_ISBN :
0-7803-1915-X
DOI :
10.1109/ISCAS.1994.409270
