Title :
A scheme for multiple on-chip signature checking for embedded SRAMs
Author :
Abdulla, M.F. ; Ravikumar, C.P. ; Kumar, Anshul
Author_Institution :
Dept. of Comput. Sci. & Eng., Indian Inst. of Technol., New Delhi, India
Abstract :
Pseudorandom self testing of embedded memories is commonly used because of its simplicity. A novel scheme pseudorandom testing with multiple on-chip signature checking (MOSC) has been proposed. Although this scheme results in significant reductions in aliasing probability at no significant increase in area in most cases, the test area and time overhead may be excessive if the circuit contains multiple embedded RAMs of various sizes. Example of such circuits are the ASICs for the telecommunications. In this paper, we propose a Static-RAM BIST scheme, based on the MOSC scheme, which is applicable for testing chips that have multiple embedded RAMs of various sizes
Keywords :
SRAM chips; application specific integrated circuits; built-in self test; integrated circuit testing; ASIC; BIST; embedded SRAM; multiple on-chip signature checking; pseudorandom self testing; telecommunications circuit; Automatic testing; Built-in self-test; CMOS technology; Circuit faults; Circuit testing; Random access memory; Read-write memory; Size control; Telecommunications; Test pattern generators;
Conference_Titel :
European Design and Test Conference, 1997. ED&TC 97. Proceedings
Conference_Location :
Paris
Print_ISBN :
0-8186-7786-4
DOI :
10.1109/EDTC.1997.582438
