DocumentCode
3436934
Title
A new horizontal and vertical common subexpression elimination method for multiple constant multiplication
Author
Kato, Kazunari ; Takahashi, Yasuhiro ; Sekine, Toshikazu
Author_Institution
Grad. Sch. of Eng., Gifu Univ., Gifu, Japan
fYear
2009
fDate
13-16 Dec. 2009
Firstpage
124
Lastpage
127
Abstract
The common subexpression elimination (CSE) techniques address the issue of minimizing the number of adders needed to implement the multiple constant multiplication (MCM) blocks. In this paper, we propose a new CSE method using a combining horizontal and vertical technique. The proposed method searches firstly the frequency of higher order horizontal common subexpression, i.e., 3-5 bits, and then searches vertical. Our simulation results show that our method offers a good tradeoff between the implementation cost and the synthesis run-time in comparison with conventional methods.
Keywords
adders; digital arithmetic; digital signal processing chips; adders; digital signal processing; horizontal common subexpression elimination; multiple constant multiplication; vertical common subexpression elimination; Adders; Cascading style sheets; Costs; Digital signal processing; Finite impulse response filter; Frequency; IIR filters; Runtime; Signal processing algorithms; Signal synthesis;
fLanguage
English
Publisher
ieee
Conference_Titel
Electronics, Circuits, and Systems, 2009. ICECS 2009. 16th IEEE International Conference on
Conference_Location
Yasmine Hammamet
Print_ISBN
978-1-4244-5090-9
Electronic_ISBN
978-1-4244-5091-6
Type
conf
DOI
10.1109/ICECS.2009.5410955
Filename
5410955
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