Title :
Design of partially parallel scan chain
Author :
Higami, Yoshinobu ; Kinoshita, Kozo
Author_Institution :
Dept. of Appl. Phys., Osaka Univ., Japan
Abstract :
This paper presents a design-for-testability technique, called partially parallel scan chain (PPSC), which aims at reduction of test length for sequential circuits. Since the partially parallel scan chain allows to control and observe subset of flip-flops (FFs) concurrently during scan shift operations, the number of scan shift clocks is reduced
Keywords :
design for testability; flip-flops; logic design; logic testing; sequential circuits; design; design for testability; flip-flop; partially parallel scan chain; scan shift clock; sequential circuit; test length; Benchmark testing; Circuit faults; Circuit testing; Clocks; Fault detection; Flip-flops; Notice of Violation; Physics; Sequential analysis; Sequential circuits;
Conference_Titel :
European Design and Test Conference, 1997. ED&TC 97. Proceedings
Conference_Location :
Paris
Print_ISBN :
0-8186-7786-4
DOI :
10.1109/EDTC.1997.582439
