Title :
The input pattern fault model and its application
Author :
Blanton, R.D. ; Hayes, John P.
Author_Institution :
Dept. of Electr. & Comput. Eng., Carnegie Mellon Univ., Pittsburgh, PA, USA
Abstract :
The input pattern (IP) fault model is a functional fault model that allows for both complete and partial functional verification of every circuit primitive, independent of the design level. Here, we formalize the model and provide a method for analyzing IP faults using single stuck-line (SSL) based tools
Keywords :
fault diagnosis; integrated circuit modelling; integrated circuit testing; logic testing; functional verification; input pattern fault model; integrated circuit; single stuck-line model; Adders; Automatic test pattern generation; Circuit faults; Circuit testing; Electrical fault detection; Equivalent circuits; Fault detection; Integrated circuit modeling; Redundancy; Semiconductor device modeling;
Conference_Titel :
European Design and Test Conference, 1997. ED&TC 97. Proceedings
Conference_Location :
Paris
Print_ISBN :
0-8186-7786-4
DOI :
10.1109/EDTC.1997.582441
