Title :
Extension of the boundary-scan architecture and new idea of BIST for more effective testing and self-testing of interconnections
Author_Institution :
Silesian Tech. Univ., Gliwice, Poland
Abstract :
The approach presented in this paper enables more effective testing of on-board and board-to-board interconnections and significantly simplifies the interconnection self-testing. Some extensions must be added to the Boundary Scan Architecture which, however, do not violate the JTAG/IEEE1149.1 standard requirements. Benefits are the reduced complexity and cost of an on-board testing unit as well as better test performance
Keywords :
boundary scan testing; built-in self test; integrated circuit interconnections; integrated circuit testing; BIST; JTAG/IEEE1149.1 standard; board-to-board interconnection; boundary-scan architecture; on-board interconnection; self-testing; testing; Automatic testing; Built-in self-test; Clocks; Compaction; Costs; Delay; Fault detection; Integrated circuit testing; Performance evaluation; System testing;
Conference_Titel :
European Design and Test Conference, 1997. ED&TC 97. Proceedings
Conference_Location :
Paris
Print_ISBN :
0-8186-7786-4
DOI :
10.1109/EDTC.1997.582443
