Low-voltage CMOS voltage squarer

A voltage squarer based on bulk-driven PMOS transistors is proposed in this paper. Circuit topology employs a voltage attenuator and the quadratic I_D/V_G characteristic of a MOS in saturation. The squarer was designed with a 0.8 V supply voltage using standard 0.35 um CMOS process, which offers large value of threshold voltage. The squarer topology was modified for 0.18 um CMOS process, which threshold voltage was smaller, operating under the extreme low supply voltage of 0.5 V. The output current is proportional to square of the input voltage in each case. Simulation results verify the theoretical analysis demonstrating small relative error and fast transient response.