Bitline Leakage Current Compensation Circuit for High-Performance SRAM Design

The leakage current existing in the bitline of SRAM has attracted more and more concerns for the operation of high-performance SRAM design, especially with the decrease of the threshold voltage of the transistor for high-performance demand, the leakage current would increase exponentially. The increased leakage current may slowdown the performance of the read operation of SRAM because the existence of the leakage current in the bitline may postpone the time to resolve the sufficient differential bitline voltage for SA to sense correctly. In this paper, a new bitline leakage current compensation circuit has been proposed. Different from the traditional technique, the proposed bitline leakage current compensation circuit cancels the "pre-determined" leakage current compensation process. Therefore, it dodges the dilemma where the performance of the SRAM may be degraded in some circumstances if the bit-line leakage current is compensated pre-determinedly. The simulation results show that by adopting the proposed compensation circuit, the time needed to develop 1/2 VDD can be reduced by almost 126.4% under the tt process corner.