DocumentCode :
3437080
Title :
On the Analysis of Reversible Booth´s Multiplier
Author :
Sultana, J. ; Mitra, S.K. ; Chowdhury, A.R.
Author_Institution :
Dept. of Comput. Sci. & Eng., Univ. of Dhaka, Dhaka, Bangladesh
fYear :
2015
fDate :
3-7 Jan. 2015
Firstpage :
170
Lastpage :
175
Abstract :
Reversible logic attains the attraction of researchers in the last decade mainly due to low-power dissipation. Designers´ endeavors are thus continuing in creating complete reversible circuits consisting of reversible gates. This paper presents a design methodology for the realization of Booth´s multiplier in reversible mode. Booth´s multiplier is considered as one of the fastest multipliers in literature and we have shown an efficient design methodology in reversible paradigm. The proposed architecture is capable of performing both signed and unsigned multiplication of two operands without having any feedbacks, whereas existing multipliers in reversible mode consider loop which is strictly prohibited in reversible logic design. Theoretical underpinnings, established for the proposed design, show that the proposed circuit is very efficient from reversible circuit design point of view.
Keywords :
logic design; multiplying circuits; efficient design method; reversible Booth multiplier; reversible circuit design; reversible circuits; reversible gate; reversible logic; reversible paradigm; Arrays; Delays; Equations; Logic gates; Microprocessors; Vectors; Booth´s Multiplier; Garbage Output; Low power Design; Quantum Cost;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
VLSI Design (VLSID), 2015 28th International Conference on
Conference_Location :
Bangalore
ISSN :
1063-9667
Type :
conf
DOI :
10.1109/VLSID.2015.34
Filename :
7031727
Link To Document :
بازگشت