Architecture of a high-rate VLSI Viterbi decoder

The Viterbi algorithm is widely applied to problems of the state estimation of a finite-state discrete-time Markov process, such as convolutional and trellis decoding. Although conventional Viterbi decoders process all states concurrently, the sequential nature of this algorithm limits the decoding throughput for a given integrated circuit technology and thereby restricts its applications. This paper presents the architecture of a single-chip Viterbi decoder combining two methods to speed-up the data rate: the “radix” trellis method and the interleaved method. The resulting architecture is very attractive for applications where high-speed decoding is essential, such as satellite digital communication systems