A systematic approach to SER estimation and solutions

Author

Nguyen, Hang T. ; Yagil, Yoad

Author_Institution

Intel Corp., Chandler, AZ, USA

fYear

2003

fDate

30 March-4 April 2003

Firstpage

60

Lastpage

70

Abstract

This paper describes a method for estimating Soft Error Rate (SER) and a systematic approach to identifying SER solutions. Having a good SER estimate is the first step in identifying if a problem exists and what measures are necessary to solve the problem. In this paper, a high performance processor is used as the base framework for discussion since it contains most, if not all, commonly used micro-architecture and circuit techniques associated with any state-of-the-art design. The framework provides a guideline for users to follow and to apply appropriate judgment to their particular problem. One major finding in this paper is that latches/flip-flops and combinational logic contribute significantly to the overall chip Failure-In-Time (FIT) rate. We also discuss potential SER techniques to combat this revelation.

Keywords

CMOS digital integrated circuits; alpha-particle effects; combinational circuits; failure analysis; flip-flops; integrated circuit reliability; integrated circuit testing; microprocessor chips; neutron effects; SER estimation; alpha particles; chip failure-in-time rate; circuit techniques; combinational logic; dynamic CMOS circuits; flip-flops; high performance processor; latches; logic derating; micro-architecture techniques; neutrons; soft error rate; static CMOS gates; systematic approach; timing derating; Alpha particles; Combinational circuits; Error analysis; Error correction; Guidelines; Latches; Logic; Neutrons; Single event upset; Space technology;

fLanguage

English

Publisher

ieee

Conference_Titel

Reliability Physics Symposium Proceedings, 2003. 41st Annual. 2003 IEEE International

Print_ISBN

0-7803-7649-8

Type

conf

DOI

10.1109/RELPHY.2003.1197722

Filename

1197722