DocumentCode :
3437261
Title :
Transmission line pulse picosecond imaging circuit analysis methodology for evaluation of ESD and latchup
Author :
Weger, Alan ; Voldman, Steven ; Stellari, Franco ; Song, Peilin ; San, Pia ; McManus, Moyra
Author_Institution :
IBM T. J. Watson Res. Center, Yorktown Heights, NY, USA
fYear :
2003
fDate :
30 March-4 April 2003
Firstpage :
99
Lastpage :
104
Abstract :
This paper will demonstrate the synthesis of the high current pulse source method (e.g. used in transmission line pulse (TLP) systems) and the Picosecond Imaging Circuit Analysis (PICA) tool for the evaluation. of electrostatic discharge (ESD) and latchup phenomenon. In this fashion, the evolution of ESD and latchup can be evaluated in semiconductor devices, and in peripheral circuits at a wafer level or product level. The methodology described in this publication allows for visualization of ESD and latchup, events (e.g. animation in a picosecond time regime). The synthesis of the transmission line pulse (TLP) method and the PICA method allows for the extension of the ESD TLP methodology to terminal currents and spatial and time domain analysis for electrical characterization and reliability analysis, and the high current pulsed source extends the utilization of the PICA methodology for failure analysis on wafer and chip levels.
Keywords :
CMOS integrated circuits; electrostatic discharge; failure analysis; high-frequency transmission lines; integrated circuit reliability; integrated circuit testing; photoelectron microscopy; pulse measurement; ESD; PICA methodology; animation; electrical overstress; electrostatic discharge; failure analysis; high current pulse source method; latchup; latchup event visualization; peripheral circuits; picosecond imaging circuit analysis tool; product level; reliability analysis; semiconductor devices; spatial domain analysis; terminal currents; time domain analysis; transmission line pulse picosecond imaging circuit analysis methodology; wafer level; Animation; Circuit analysis; Circuit synthesis; Distributed parameter circuits; Electrostatic discharge; Failure analysis; Pulse circuits; Semiconductor devices; Time domain analysis; Visualization;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Reliability Physics Symposium Proceedings, 2003. 41st Annual. 2003 IEEE International
Print_ISBN :
0-7803-7649-8
Type :
conf
DOI :
10.1109/RELPHY.2003.1197727
Filename :
1197727
Link To Document :
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