Title :
A device level negative feedback in the emitter line of SCR-structures as a method to realize latch-up free ESD protection
Author :
Concannon, A. ; Vashchenko, V.A. ; ter Beek, M. ; Hopper, P.
Author_Institution :
Nat. Semicond. Corp., Santa Clara, CA, USA
fDate :
30 March-4 April 2003
Abstract :
The practical goal of this study is to develop an efficient design solution for the control of the holding voltage of thyristor-type structures (ones operating in the left part of S-shape I-V characteristic), thereby making them suitable for use in mixed-signal and in power supply protection circuits. This specific design is applied to the cascoded LVTSCR structures and validated on the basis of ESD test structures and I/O cells. The research objective was to control the avalanche-injection conductivity modulation by the emitter injection of the device level, thereby achieving control of the section of the S-shape I-V curve responsible for the holding voltage.
Keywords :
CMOS integrated circuits; circuit feedback; electrostatic discharge; integrated circuit reliability; integrated circuit testing; protection; technology CAD (electronics); thyristor applications; 0.18 micron; 1.8 V; 3.3 V; CMOS technology; ESD test structures; I/O cells; S-shape I-V characteristic; SCR-structures; avalanche-injection conductivity modulation; cascoded LVTSCR structures; design solution; device level negative feedback; emitter line; holding voltage control; latch-up free ESD protection; mixed-signal circuits; power supply protection circuits; technology CAD analysis; thyristor-type structures; Anodes; Cathodes; Circuits; Clamps; Conductivity; Electrostatic discharge; Negative feedback; Protection; Thyristors; Voltage control;
Conference_Titel :
Reliability Physics Symposium Proceedings, 2003. 41st Annual. 2003 IEEE International
Print_ISBN :
0-7803-7649-8
DOI :
10.1109/RELPHY.2003.1197728
