Title :
Adaptative backtrace and dynamic partitioning enhance ATPG [IC testing]
Author_Institution :
Dept. of Autom. & Inf., Polytech. of Turin, Italy
Abstract :
Two improvements to existing automatic-test-pattern-generation (ATPG) algorithms are proposed. First, an adaptive technique has been introduced to solve internal conflicts in the backtrace phase of previous algorithms. This has proved useful in reducing the number of backtracks, allowing tests to be generated faster and more redundancies to be identified. In addition, to cope with the large size of present VLSI circuits, the author has also proposed to dynamically identify useless regions, which can be dropped from consideration. This way it has been possible to considerably speed up the overall test generation tasks. An ATPG system based on these ideas has been developed and it has proved effective in generating test for large circuits
Keywords :
VLSI; automatic testing; integrated circuit testing; logic testing; redundancy; VLSI circuits; adaptive backtrace; automatic-test-pattern-generation; backtracks; dynamic partitioning; gate level test generation; large circuits; redundancies; Automatic test pattern generation; Automatic testing; Circuit faults; Circuit testing; Design for testability; Digital circuits; Integrated circuit testing; Partitioning algorithms; Sequential analysis; System testing;
Conference_Titel :
Computer Design: VLSI in Computers and Processors, 1988. ICCD '88., Proceedings of the 1988 IEEE International Conference on
Conference_Location :
Rye Brook, NY
Print_ISBN :
0-8186-0872-2
DOI :
10.1109/ICCD.1988.25660
