Title :
Instruction reorganization for a variable-length pipelined microprocessor
Author :
Abraham, Seth ; Padmanabhan, Krishnan
Author_Institution :
Dept. of Comput. Sci., Illinois Univ., Urbana, IL, USA
Abstract :
The implementation of an instruction reorganizer for a floating-point microprocessor with a variable-length pipeline is described. The reorganizer is designed to work with compiler-generated or hand-written assembly language code. A greedy heuristic algorithm is used to reorder instructions inside basic blocks. Memory aliasing is handled by accepting dependency-resolving directives from either the compiler or the assembly language programmer. Benchmark of the reorganizer using the Basic Linear Algebra Subprograms and the Livermore Loops are presented
Keywords :
microprocessor chips; pipeline processing; program compilers; Basic Linear Algebra Subprograms; Livermore Loops; dependency-resolving directives; floating-point microprocessor; greedy heuristic algorithm; instruction reorganizer; memory aliasing; variable-length pipeline; variable-length pipelined microprocessor; Artificial intelligence; Assembly systems; Computer aided instruction; Computer architecture; Computer science; Laboratories; Microprocessors; Pipelines; Program processors; Programming profession;
Conference_Titel :
Computer Design: VLSI in Computers and Processors, 1988. ICCD '88., Proceedings of the 1988 IEEE International Conference on
Conference_Location :
Rye Brook, NY
Print_ISBN :
0-8186-0872-2
DOI :
10.1109/ICCD.1988.25667
