Cache-based pipeline architecture in the Hitachi H32/200 32-bit microprocessor

Author

Nishimukai, T. ; Inayoshi, H. ; Takagi, K. ; Iwasaki, K. ; Kawasaki, I. ; Hanawa, Masanori ; Okada, T.

Author_Institution

Hitachi Ltd., Tokyo, Japan

fYear

1988

fDate

3-5 Oct 1988

Firstpage

102

Lastpage

105

Abstract

A stack cache scheme in combination with a general register set is presented as an alternative to the register file. Two cache memories, a 1-K byte code cash and a four-entry cache for branch instructions, are also embedded to accelerate the pipeline stream. This scheme has been implemented and evaluated on a 32-bit microprocessor, the Hitachi H32/200, based on TRON (The Real-time Operating system Nucleus) specifications. This processor contains 730 K transistors in 1.0-μm CMOS. It performs 6 to 7 MIPS (million instruction per second) at a 20-MHz clock rate

Keywords

buffer storage; computer architecture; microprocessor chips; pipeline processing; storage management; 1-K byte code cash; 20 MHz; 20-MHz clock rate; 32 bit; 32-bit microprocessor; 7 MIPS; Hitachi H32/200; Real-time Operating system Nucleus; branch instructions; cache memories; four-entry cache; general register set; register file; stack cache scheme; Acceleration; Cache memory; Delay; Hardware; Laboratories; Microprocessors; Pipelines; Reduced instruction set computing; Registers; Switches;

fLanguage

English

Publisher

ieee

Conference_Titel

Computer Design: VLSI in Computers and Processors, 1988. ICCD '88., Proceedings of the 1988 IEEE International Conference on

Conference_Location

Rye Brook, NY

Print_ISBN

0-8186-0872-2

Type

conf

DOI

10.1109/ICCD.1988.25670

Filename

25670