Title :
Design tradeoffs for a 40 MIPS (peak) CMOS 32-bit microprocessor
Author :
Lewis, D.K. ; Costello, J.P. ; O´Connor, D.M.
Author_Institution :
GE Aerosp. Lab., Syracuse, NY, USA
Abstract :
The RPM40 32-bit CMOS microprocessor system and its initial architectural design tradeoffs are presented. The system is based around two custom VLSI chips, a CPU and an FPU, and has demonstrated programs operating at a 40-MIPS (million-instruction-per-second) peak rate for CPU integer operations. This peak rate is achieved when the CPU pipeline is full, without NOPS, and ignoring cache misses. The peak rate is achieved for many segments of code by careful reorganization of instructions
Keywords :
CMOS integrated circuits; VLSI; computer architecture; microprocessor chips; 32 bit; 40 MIPS; CMOS 32-bit microprocessor; CPU integer operations; FPU; RPM40; architectural design tradeoffs; instruction reorganization; Application software; CMOS technology; Coprocessors; Delay; Laboratories; Microprocessors; Packaging; Random access memory; System-on-a-chip; Very large scale integration;
Conference_Titel :
Computer Design: VLSI in Computers and Processors, 1988. ICCD '88., Proceedings of the 1988 IEEE International Conference on
Conference_Location :
Rye Brook, NY
Print_ISBN :
0-8186-0872-2
DOI :
10.1109/ICCD.1988.25672
