Title :
Extension of a transistor level digital timing simulator to include first order analog behavior
Author :
Chadha, Rakesh ; Chen, Chin-Fu
Author_Institution :
AT&T Bell Lab., Murray Hill, NJ, USA
Abstract :
The simulator is built on the second-generation MOTIS mixed-mode simulator to accommodate simulation for analog circuits. It uses circuit-simulation techniques for the analog portions of the chip, and timing and logic simulation techniques for the digital portions. The simulator can be used for overall design verification of a chip at the transistor level
Keywords :
analogue circuits; circuit analysis computing; digital integrated circuits; digital simulation; logic CAD; analog circuits; circuit-simulation techniques; design verification; first order analog behavior; logic simulation techniques; second-generation MOTIS mixed-mode simulator; transistor level digital timing simulator; Analog circuits; Capacitance; Circuit simulation; Delay; Design methodology; Digital circuits; Logic circuits; MOSFETs; Timing; Very large scale integration;
Conference_Titel :
Computer Design: VLSI in Computers and Processors, 1988. ICCD '88., Proceedings of the 1988 IEEE International Conference on
Conference_Location :
Rye Brook, NY
Print_ISBN :
0-8186-0872-2
DOI :
10.1109/ICCD.1988.25673
