Title :
A 0.0027-mm2 9.5-bit 50-MS/s all-digital A/D converter TAD in 65-nm digital CMOS
Author :
Watanabe, Takamoto ; Yamauchi, Shigenori ; Terasawa, Tomohito
Author_Institution :
Corp. R&D Dept. 2, Denso Corp., Kariya, Japan
Abstract :
An all-digital A/D converter TAD (time A/D converter) with 0.0027 mm2 is presented. The circuit structure is completely digital including a pulse-delay-line driven by Vin (input voltage), along with a counter, latch, and encoder. The TAD is easily shrinkable with the advancement in CMOS process technologies without any change of circuit architecture. Thanks to this construction, A/D conversion resolution with TAD method can automatically be improved. Their voltage resolutions of design rules from 0.8 ¿m to 65 nm are experimentally confirmed and compared, resulting in 80 times higher resolution of 65-nm TAD than that of 0.8-¿m TAD. At the same time, the TAD core size is reduced less than 1/100. The unique TAD feature is that its resolution is settable by selecting sampling rates and power consumption is very low. For example, a prototype IC with 65-nm digital CMOS with 1.2-V supply voltage achieved 18.4-bit at 100-kS/s (1.11 mW), 10.8-bit 20-MS/s (1.13 mW), and 9.5-bit 50-MS/s (1.18 mW), respectively.
Keywords :
CMOS digital integrated circuits; analogue-digital conversion; delay circuits; CMOS process; all-digital A/D converter TAD; circuit architecture; circuit structure; digital CMOS; power consumption; pulse-delay-line; size 0.8 mum; size 65 nm; time A/D converter; CMOS integrated circuits; CMOS process; CMOS technology; Counting circuits; Energy consumption; Latches; Prototypes; Pulse circuits; Sampling methods; Voltage;
Conference_Titel :
Electronics, Circuits, and Systems, 2009. ICECS 2009. 16th IEEE International Conference on
Conference_Location :
Yasmine Hammamet
Print_ISBN :
978-1-4244-5090-9
Electronic_ISBN :
978-1-4244-5091-6
DOI :
10.1109/ICECS.2009.5410988
